Current methods of transmitting digital data between components on a motherboard (for example, between a chipset and a processor) use transmission lines. As data rates increase in proportion to Moore's Law, signals propagating on the transmission line are dramatically attenuated due to the low-pass filter behavior of the transmission line structure.
FIG. 1 illustrates a graph 100 depicting the behavior of a traditional transmission line. As evident in FIG. 1, it is noted that high frequencies are attenuated, which causes a large roadblock to designing high speed digital systems. An interconnect with the behavior illustrated in FIG. 1 allows data transmission up to approximately 20 Gb/sec (gigabits per second), with a fundamental frequency of approximately 10 GHz (gigahertz). Above this data rate the harmonic components of the digital waveform would be so attenuated that the signal is not recoverable at the receiver end of the transmission line. For example, at 20 Gb/sec (10 GHz fundamental frequency), the signal is attenuated to approximately −20 dB (decibels) (approximately 10% of the original signal), and at 40 Gb/sec (20 GHz fundamental frequency), the signal is attenuated to approximately −30 dB (decibels) (approximately 3% of the original signal). Signals attenuated at this level are not typically recoverable at the receiver. Therefore, as data rates have increased, a need has arisen for an ultra-high bandwidth, low loss, cost effective interconnect that can be used to transmit digital data between components on a digital system (for example, on a printed circuit board such as a motherboard).